This invention relates to electronic circuits, and more particularly relates to an improved input transition stabilizer circuit.
Integrated circuit technology allows the fabrication of integrated circuit xe2x80x9cchipsxe2x80x9d including thousands of devices. In this way, very complex circuits can be implemented in packages having a very small size. However, placing many devices in a small area can give rise to problems. One problem that sometimes occurs is the presence of xe2x80x9cglitches,xe2x80x9d or unintended reversals of logic state at the inputs to such integrated circuits, leading to erroneous results at the outputs of the circuits. Such glitches can occur as a result of the large signal swing at an output of the circuit coupling to either or both of the voltage supply, VCC, and the circuit ground, through, for example, package parasitic reactance. The resulting swing in the voltage of VCC and/or ground is sometimes called xe2x80x9cVCC bouncexe2x80x9d or xe2x80x9cground bounce,xe2x80x9d respectively. When this voltage bounce appears at the VCC and/or ground of an input circuit, such as an input buffer, a glitch can occur, for example as the input buffer is pinched off during an input signal transition. This is especially true for circuits receiving an input having a slow input transition, or xe2x80x9cramp rate.xe2x80x9d
FIG. 1 is a diagram showing a simplified circuit 100, illustrating ground bounce. The circuit has a pair of input terminals 101, the non-ground terminal of which is connected to one terminal of an electrostatic discharge (ESD) resistor 102. The other terminal of resistor 102 is connected to the input of an inverting input buffer 103. The output of the inverting input buffer 103 is connected to other circuitry (not shown), the output of which is connected to the input of an output buffer 104. The output of output buffer 104 is connected to the non-ground terminal of a pair of output terminals 105. As shown, a voltage swing on the ground terminal of output terminal 105 can couple back 106 to the ground of the input buffer 103, resulting in an unwanted glitch, as described above.
To alleviate this problem, a dynamic hysteresis circuit xe2x80x9cDHCxe2x80x9d is sometimes used. FIG. 2 is a diagram showing a simplified circuit 200, like circuit 100 of FIG. 1, but also including a DHC 107. As can be seen, DHC 107 is connected between the output of input buffer 103 and ground. The DHC 107 operates to activate a xe2x80x9cholding transistorxe2x80x9d when the output of input buffer 103 initially switches. This holding transistor holds the node in the new state if the input buffer 103 is disturbed and momentarily starts to switch back to the previous state, i.e., outputs a glitch. The DHC 107 also has a delay portion through which the signal propagates. After a signal propagates through the delay portion of the DHC 107, the DHC 107 is turned off.
The DHC solution is effective to prevent glitches from propagating to the output of a circuit. However, it can add an undesirable propagation delay to the overall circuit. In addition, a DHC can be sensitive to power supply current (ICC) versus frequency tests, and if not properly designed can cause the overall circuit to malfunction at certain frequencies. The DHC is connected to the output of the input buffer; if the frequency of operation of the overall circuit is fast enough that the input signal switches again, as part of its normal operation, before the DHC times out, the holding transistor of the DHC can remain active and affect the speed of the node to which it is connected.
It would therefore be desirable to have a solution to the problem of glitches, while overcoming the problems of the prior art.
In accordance with the present invention, there is provided an input transition stabilizer circuit, adapted to stabilize an input transition of a signal appearing at the input of an input circuit, the input transition stabilizer circuit includes a resistor having a first terminal connected to the input of the input circuit;, and a capacitor. A first MOS device is connected by a source and a drain between a second terminal of the resistor and a first terminal of the capacitor, while a second MOS device is connected by a source and a drain between a second terminal of the capacitor and ground. A delay circuit is adapted to provide a signal to a gate of the first MOS device and a gate of the second MOS device corresponding to a signal at the input of the input circuit, but delayed by a first predetermined interval. In some embodiments the delay circuit is provided in two parts, with the signal provided to the first MOS device being delayed by a further amount, as compared with the signal provided to the second MOS device.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.